Modern data processing systems use binary numbers for the computation of data. This computation includes both integer arithmetic and floating-point arithmetic. Floating point arithmetic, used in addition, multiplication, and division, first normalizes the binary numbers to be added, multiplied, or divided by shifting the binary numbers until the first non-zero digit (i.e. 1) is immediately to the left of the radix point such that the mantissa part of binary numbers will be greater than or equal to 1 and less than 2. For multiplication the normalized binary numbers are then multiplied and their exponents added. For division, the normalized binary numbers are divided and their exponents subtracted.
To normalize a binary number, the number of leading zeros (i.e., the number of zeros to the left of the first 1 in the binary number) should be quickly determined so that the number of shifts of the binary number can be quickly performed. Floating point multiplication and division calculations are typically reiterative and, thus, for a single multiplication or division calculation, the leading zeros at each step in the reiterative process should be calculated. Hence, any delays in counting these leading zeros are accumulated many times during a single multiplication or division calculation.
It is known that special count leading zero (CLZ) circuits are provided as part of the microprocessor for counting or detecting leading zeros within a binary number. It is also well known that speed and circuit size are two critical parameters in the design of any microprocessor. Often, these two parameters are mutually exclusive in that a faster microprocessor or components thereof operate faster when employing large complex circuitry but which have the disadvantage of occupying a large area within the integrated circuit. Prior art circuits for detecting or counting leading zeros within binary numbers are subject to this principle.
It would therefore be desirable to produce a count leading zero circuit that achieves a significant reduction in the number of clock cycles required to produce a leading zero count and that also decreases the amount of area required to implement the circuit.